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Freescale Semiconductor /MKL05Z4 /ADC0 /CFG1

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Interpret as CFG1

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (00)ADICLK 0 (00)MODE 0 (0)ADLSMP 0 (00)ADIV 0 (0)ADLPC

ADLSMP=0, ADICLK=00, ADLPC=0, MODE=00, ADIV=00

Description

ADC Configuration Register 1

Fields

ADICLK

Input Clock Select

0 (00): Bus clock

1 (01): (Bus clock)/2

2 (10): Alternate clock (ALTCLK)

3 (11): Asynchronous clock (ADACK)
MODE

Conversion mode selection

0 (00): It is single-ended 8-bit conversion.

1 (01): It is single-ended 12-bit conversion .

2 (10): It is single-ended 10-bit conversion .

3 (11): Reserved. Do not set the bitfield to this value.
ADLSMP

Sample time configuration

0 (0): Short sample time.

1 (1): Long sample time.
ADIV

Clock Divide Select

0 (00): The divide ratio is 1 and the clock rate is input clock.

1 (01): The divide ratio is 2 and the clock rate is (input clock)/2.

2 (10): The divide ratio is 4 and the clock rate is (input clock)/4.

3 (11): The divide ratio is 8 and the clock rate is (input clock)/8.
ADLPC

Low-Power Configuration

0 (0): Normal power configuration.

1 (1): Low-power configuration. The power is reduced at the expense of maximum clock speed.

Links

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Register License

Redistribution and use in source and binary forms, with or without modification,\nare permitted provided that the following conditions are met:\n o Redistributions of source code must retain the above copyright notice, this list\n of conditions and the following disclaimer.\n o Redistributions in binary form must reproduce the above copyright notice, this\n list of conditions and the following disclaimer in the documentation and/or\n other materials provided with the distribution.\n o Neither the name of Freescale Semiconductor, Inc. nor the names of its\n contributors may be used to endorse or promote products derived from this\n software without specific prior written permission.\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS “AS IS” AND\n ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR\n ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON\n ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data